In U.S. Pat. No. 4,105,475 to Jenne, there is shown a semiconductor device having an array of single transistor VMOS memory cells. Each of the cells includes a storage capacitor region in a substrate with a V-shaped recess extending thereinto and having the oxide of a gate element on its walls. A drain region of each of the memory cells is in surrounding relation to the V-shaped recess and closer to the upper end of the channel region of the gate element than the lower end.
One problem with the VMOS memory cell of the aforesaid Jenne patent is that it requires a buried storage capacitor if the semiconductor device is to have a relatively high density of the VMOS memory cells thereon. However, this requires an additional processing step.
Another problem with the VMOS memory cell of the aforesaid Jenne patent is that the gate oxide has a tendency to break down at the bottom of the V-shaped recess when subjected to a relatively low voltage. This point breakdown of the gate oxide causes the storage cell to cease to function properly.
A further problem with the VMOS memory cell of the aforesaid Jenne patent is that it depends upon an outdiffusion during growth of an epitaxial layer to control the threshold voltage between the gate channel region and the substrate. Thus, it is a requisite of the VMOS memory cell of the aforesaid Jenne patent that the substrate include an epitaxial layer.
The present invention overcomes the foregoing problems of the aforesaid Jenne patent in that there is no requirement for any buried storage capacitor. There also is no point formed for the gate oxide so that the point breakdown of the gate oxide is eliminated. The present invention also does not require the growth of an epitaxial layer to control the threshold voltage since it utilizes an ion implantation to control the threshold voltage. It is not possible to implant ions in a VMOS memory cell at the time that such is required to control the threshold voltage.
Additionally, the present invention also has a substantially higher density of memory cells in comparison with the density of the VMOS memory cells.
One means of increasing the charge storage region of a memory cell is through forming an enlarged wall in the substrate and is shown in the aforesaid Fatula et al application. In the aforesaid Fatula et al application, the drain and source regions are formed in the surface of the substrate with the charge storage region being beneath the drain region.
The present invention is an improvement of the aforesaid Fatula et al application in that only one of the drain and source regions is formed in the surface of the substrate. Thus, the density of the memory cells of the present invntion can be increased beyond the memory cell density of the structure of the aforesaid Fatula et al application.